Papers on logic design in Czech - tutorials on logic design

Series on implementation of counters

• J. Šťastný. Implementace čítačů v číslicových systémech 1, DPS Plošné spoje od A do Z, no 3, pp. 20-23, 2011.
• J. Šťastný. Implementace čítačů v číslicových systémech 2, DPS Plošné spoje od A do Z, no 4, pp. 11-14, 2011.
• J. Šťastný. Implementace čítačů v číslicových systémech 3, DPS Plošné spoje od A do Z, no 5, pp. 18-20, 2011.

Series on assertions (PSL, VHDL flavor)

• J. Šťastný. Verifikace pomocí assertions: seznámení, DPS Elektronika od A do Z, no 6, pp. 4-8, 2012.
• J. Šťastný. Verifikace pomocí assertions: jazyk PSL, DPS Elektronika od A do Z, no 2, pp. 30-34, 2013.
• J. Šťastný. Verifikace pomocí assertions: případové studie, DPS Elektronika od A do Z, no 3, pp. 10-13, 2013.
• J. Šťastný. Verifikace pomocí assertions: jak začít, DPS Elektronika od A do Z, no 4, pp. 4-9, 2013.

Series on digital simulation - principles as well as advanced concepts

• J. Šťastný. Simulace číslicových obvodů: úvod, DPS Elektronika od A do Z, pp. 23-27, leden/únor 2015
• J. Šťastný. Simulace číslicových obvodů: triky i úskalí simulace, DPS Elektronika od A do Z, pp. 20-23, březen/duben 2015
• J. Šťastný. Simulace číslicových obvodů na hradlové úrovni, DPS Elektronika od A do Z, pp. 8 - 11, květen/červen 2015
• J. Šťastný. Simulace číslicových obvodů na hradlové úrovni: model návrhu, DPS Elektronika od A do Z, pp. 6 - 12, leden/únor 2016
• J. Šťastný. Simulace číslicových obvodů na hradlové úrovni: dobrá praxe, DPS Elektronika od A do Z, pp. 14 - 18, březen/duben 2016

Others

• J. Šťastný. Výhody použití datového typu record v syntetizovatelném VHDL, DPS Elektronika od A do Z, no 4, pp. 56-61, 2024.
• J. Šťastný. The advantages of the usage of the record data type in the synthesizable HDL code, DPS Elektronika od A do Z, no 4, pp. 56-61, 2024. (English translation of the Czech paper).
• J. Šťastný, M. Skiba. Precision RTL a konverze ASIC obvodu na FPGA platformu, DPS Plošné spoje od A do Z, no 2, pp. 4-6, 2010.
• J. Šťastný. Od algoritmu k číslicovému obvodu, DPS Plošné spoje od A do Z, no 1, pp. 14-18, 2012.

Current Lectures/Aktuální přednášky

• Simulace číslicových obvodů, 4.3.2024, FEKT VUT Brno, předmět Digitální integrované obvody
  • Přednáška
  • Doporučená literatura - viz níže
  • Co byste po této přednášce měli znát
    • úrovně abstrakce používané při návrhu číslicových systémů, návrh jako postupné zpřesňování modelu systému
    • typická podoba návrhu v simulátoru - hierarchie bloků
    • simulace na hradlové úrovni - proč je užitečná, co je k ní třeba
    • měření pokrytí obvodu simulátorem - metriky a jejich význam
    • použití náhodných čísel při verifikaci - základní principy
    • a letošní bonus: k čemu jsou dobré signály typu record ("rekordy") v syntetizovatelném VHDL :-)
• Synchronizace asynchronních signálů, mezidoménové přechody, implementace resetu obvodu, 4.12.2024, FIT VUTBR
  • Přednáška
  • Doporučená literatura - viz níže
  • Co byste po této přednášce měli znát
    • časové parametry klopných obvodů
    • postupy pro kontrolu dodržení předstihu a přesahu v synchronním číslicovém obvodu, typické případy kdy dochází k porušení jednotlivých parametrů
    • techniky pro dosažení správného časování (jak se řeší na FPGA a ASIC obvodu nedodržení předstihu a přesahu)
    • techniky pro práci s jednobitovým asynchronním signálem - data a reset
    • techniky pro práci s vícebitovými asynchronními signály
    • korespondenční režim a jeho vlastnosti
• Assertions v RTL návrhu, 04.11.2024, ČVUT FEL Praha, předmět Struktury integrovaných systémů
  • Slídy - verifikace číslicových obvodů a assertions
  • Doporučená literatura - viz níže
  • Pro připomenutí: co byste si z této přednášky měli odnést:
    • Co je to verifikace?
    • Jak typicky probíhá?
    • Black box vs white box přístup, princip: vkládám do návrhu (nesyntetizované) konstrukce použité pro kontrolu správné funkce/verifikaci, nebo pro monitorování simulovných funkcí.
    • Jakými prostředky lze takové konstrukce realizovat?
    • Directed vs Constrained random přístup
    • Kdy je verifikace dokončená? Jak to poznám?

Příklady a materiály k článkům/Examples, supplementary materials to the papers

• Simulace číslicových obvodů: úvod - příklad k článku
• Čítače - seriál pro DPS Elektronika od A do Z
• Verifikace pomocí assertions
  • Murphyho zákony, proti kterým lze bojovat pomocí assertions
    • Bugs will appear in one part of a working program when another 'unrelated' part is modified.
    • Undetectable errors are infinite in variety, in contrast to detectable errors, which by definition are limited.
    • The documented interfaces between standard modules will have undocumented quirks.
    • A working design is one that has only unobserved bugs.
    • Every non-trivial program contains at least one bug. Every non-trivial program can be simplified by at least one line of code.
      The conclusion of the last two laws: Every non trivial program can be simplified to one line of code, and it will contain a bug.
    • If a project is completed on schedule, it wasn't debugged properly.
  • Příklady k druhému dílu - seznámení s jazykem PSL - VHDL kód

Recommended reading

Assertions, Verification

Some books

• Harry Foster, Adam Kolnik, David Lacey. Assertion Based Design, 2nd edition. 2003 Kluwer Academic Publishers
• Janick Bergeron, Writing Testbenches: Functional Verification of HDL Models.

Web resources

• Doulos. PSL tutorial.
• Another PSL language tutorial
• Specifikace PSL 1.1 (a bit older, but still can be useful)
• UVM - Universal Verification Methodology
• OVL - Open Verification Library
• Verification Academy - Mentor Graphic's site on Verification

Interesting papers, blog posts, others

• Don Mills, Stuart Sutherland. System Verilog Assertions are for design engineers, too! In SNUG San Jose 2006.
• Charu Aggarwal, Genadi Osowiecki, Shobha Subramanian. A practical guide for deploying assertions in RTL. CDN Live, 2007.
• Clifford Cummings. SystemVerilog Assertions - Bindfiles & Best Known Practices for Simple SVA Usage.
  Best practices for the SVA usage in the design, mainly usage of bindfiles is discussed, there.
• Erich Marschner, Bernard Deadman, Grant Martin. IP Reuse Hardening via Embedded Sugar Assertions.
  Advantages of the PSL assertions in reusable code are discussed here and the paper summarizes basic PSL structures.
• Stuart Sutherland. Adding Last-Minute Assertions: Lessons Learned (a little late) about Designing for Verification. DVCon - Design and Verification Conference 2009.
  A nice case study on last-minute application of assertions - and also lots of others interesting papers.
• Gunnar Kudrjavets, Nachi Nagappan, Tom Ball. Assessing the Relationship between Software Assertions and Code Quality: An Empirical Investigation. Microsoft Technical Report MSR-TR-2006-54
  An empricial study showing a negative correlation between the number of asserions in the code and defects in the final product, i.e., the more assertions we have, the less bugs are in the code.
• B. Bentley. Validating the Intel(R) Pentium(R) 4 microprocessor. Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232), Las Vegas, NV, USA, 2001, pp. 244-248. doi: 10.1145/378239.378473
  An interesting (albeit older) case study on verification of a large digital device
• S. Taylor et al. Functional verification of a multiple-issue, out-of-order, superscalar Alpha processor-the DEC Alpha 21264 microprocessor. Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175), San Francisco, CA, USA, 1998, pp. 638-643.
  Another interesting paper (even if older) on methodology used to verify a large digital system
• DeepChip. Subject: Dan Joyce's 16 bug types only found with gate-level simulation
  A nice summary of types of bugs which can be found only by running gate-level simulations.
• DeepChip. Subject: Dan Joyce's 29 cost-effective gate-level simulation tips: Part 1, Part 2, Part 3. Tips and tricks on how to do and why is useful to do gate level simulations. A highly recommended reading :-).
• Wilson Verification study. A comprehensive and very interesting source on design trends in the semiconductor industry.
• Bertrand Meyer. Applying "Design by Contract ", in Computer (IEEE), 25, 10, October 1992, pages 40-51. Design by contract is a technique which inspired assertion-based design. Reading of this paper is thus recommended even for a hardware engineer, you can obtain a sound knowledge of the ideas behind assertion-based verification from it. You just need to abstract a bit from the object-oriented technology and find parallels with hardware design...
• Bertrand Meyer, Jean-Marc Jézéquel: Design by Contract: The Lessons of Ariane, in Computer (IEEE , vol. 30, no. 1, January 1997, pages 129-130. An interesting case study on Arian space ship crash and how design by contract could help, there.

Designing with asynchronous sigals

• D. Kinniment, "Synchronization and Arbitration in Digital Systems". Wiley 2008
  A thorough book on the synchroization of signals, passing of data between clock domains, and arbitration going from the ground up, including mathematical description of metastability.
• R. Ginosar, "Metastability and Synchronizers: A Tutorial," in IEEE Design & Test of Computers, vol. 28, no. 5, pp. 23-35, Sept.-Oct. 2011. doi: 10.1109/MDT.2011.113
  Introduction to resynchronization and synchronizer implementations including simplified model of register metastable behavior.
• R. Ginosar, "Fourteen ways to fool your synchronizer," Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings., 2003, pp. 89-96. doi: 10.1109/ASYNC.2003.1199169
  Another paper from the same author summarizing basic misunderstandings around synchronizers.
• Clifford Cummings. Synchronous Resets? Asynchronous Resets? I am so confused! How will I ever know which to use? SNUG 2003, Boston.
  A useful summary on how to handle resets in your design
• Clifford Cummings. Asynchronous & Synchronous Reset Design Techniques - Part Deux. SNUG 2002. San Jose
  How to handle resets - their proper synchronization
• Clifford Cummings. Simulation and Synthesis Techniques for Asynchronous FIFO Design
  Proper way how to design an asynchronnous FIFO
• Clifford Cummings. Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs (clock naming…)
  How to properly work with asynchronnous signals in a mutli-clock domain logic design
• S. Golson, "Synchronization and Metastability," SNUG Silicon Valley 2014
  A comprehensive survey of "everythihg important around synchronizers". I suggest to study the papers which are referred by this one, there are very interesting ones, there. NEW
• S. Beer, J. Cox, T. Chaney and D. M. Zar, "MTBF Bounds for Multistage Synchronizers," 2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems, Santa Monica, CA, USA, 2013, pp. 158-165, doi: 10.1109/ASYNC.2013.18.
  This paper gives an insight into the metastability behaviour of the full flip-flop. NEW
• Teehan, Paul & Greenstreet, Mark & Lemieux, Guy. (2007). A survey and taxonomy of GALS design styles. Design & Test of Computers, IEEE. 24. 418 - 428. 10.1109/MDT.2007.151.
  An interesting survey on the synchronization styles used in Globally Asynchronous Locally Synchronous designs with references to many other papers going in-depth.
• I. E. Sutherland. Micropipelines. Commun. ACM 32, 6 (June 1989), 720–738. DOI:https://doi.org/10.1145/63526.63532
  Description of an interesting approach to clock-less design using transition signaling.
• T. Chelcea and S. M. Nowick. Robust interfaces for mixed-timing systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 8, pp. 857-873, Aug. 2004, doi: 10.1109/TVLSI.2004.831476.
  Design of a low-latency mixed timing FIFO; the FIFO is decomposed to the interfaces and core functions and way how to combine synchrohous and asynchronous put/get operations is described. The asynchrounous interfaces are based on the same ideas as presented above in the Sutherland's Micropipeline paper.
• Antonio Cantoni, et al. Characterization of a Flip-Flop Metastability Measurement Method. IEEE Transactions on Circuits and Systems, Vol. 54, No. 5, May 2007
• Suwen Yang. Computing Synchronizer Failure Probabilities. Design, Automation and Test in Europe Conference and Exposition (DATE 2007), April 16-20, 2007, Nice, France
  An interesting paper describing an approach how to reliably simulate metastability behavior. It also summarizes some issues with usage of standard analog simulator for metastability simulation.
• C. Dike and E. Burton. Miller and noise effects in a synchronizing flip-flop. IEEE Journal of Solid-State Circuits, vol. 34, no. 6, pp. 849-855, June 1999.
  Analysis of the effect of the thermal noise on the metastable flip-flop behaviour. Two types of metastability are described there - deterministic metastability and true metastability where the thermal noise is the major contributor. Also Tw (metastability window) estimation from the measured MTBF is presented.
• Peter Alfke. XAPP094, Metastable Recovery in Virtex-II Pro FPGAs. February 10, 2005.
  A study measuring the MTBF of the Xilinx Flip-Flops in a synchronizer, also presenting the measuring circuit. Interesting case study giving some notion on how the metastability manifests itself.
• C. Maxfield. Yet another Gray code conundrum. EETimes, 19.07.2007.
  An algorithm to create a non-power-of-2 Gray code sequence.
• C. L. Portmann and H. Y. Meng. Metastability in CMOS library elements in reduced supply and technology scaled applications. IEEE Journal of Solid-State Circuits, vol. 30, no. 1, pp. 39-46, Jan. 1995, doi: 10.1109/4.350196 On the supply voltage influence on the metastabilty.
• Chaney, T. J. and C. E. Molnar. Anomalous Behavior of Synchronizer and Arbiter Circuits. IEEE Transactions on Computers C-22 (1973): 421-422. An interesting paper revealing some bits from the history of the synchronizers.
• M. Pechoucek, "Anomalous Response Times of Input Synchronizers," in IEEE Transactions on Computers, vol. C-25, no. 2, pp. 133-139, Feb. 1976, doi: 10.1109/TC.1976.5009227. Analysis of the synchronizer response time along with a proposal for a system where the clock period would be extended on demand to give the synchronizer the time to settle down.
• Harris, David Money, Ron Ho, Gu-Yeon Wei and Mark Horowitz. “The Fanout-of-4 Inverter Delay Metric.” (1998). Some papers recommend FO-4 metric as an approximation of the flip flop time constant, so here is a link to one paper on FO4 and what is it about.
• David T. Wang. Revisiting the FO4 Metric.In-depth discussion of the FO-4 metric.

General logic design

Some books

• Only in Czech: Jakub Šťastný, FPGA prakticky. BEN Praha 2010
• Only in Czech: J. Pinker, M. Poupa. Číslicové systémy a jazyk VHDL. BEN Praha 2006
• Dustin Boswell, Trevor Foucher. The Art of Readable Code. O'Reilly Media 2011
  A very good book on coding styles, with lots of hints on how to write code which is simultaneously easy to understand and the risk of a bug inserted during coding is reduced.
• NOVÁK, O., GRAMATOVÁ, E., UBAR, R. et al. Handbook of testing electronic systems. Praha: Nakladatelství ČVUT, srpen 2005, 395 stran, ISBN 80-01-03318-X
• Only in Czech:Jiří Adámek. Kódování
  A very good introduction to the theory of codes - not cryptographical, but for error correction, detection, compression. It is not easy to get this book as it is an old one, but if you manage to get it, it is really worth reading.

Interesting papers

• The Complete Digital Technical Journals - one of my colleagues pointed me to these. Complete archive of the internal journal on computer design published by Digital Equipment corporation. A bit retro, but still highly interesting reading.
• B. Hailpern and P. Tarr, "Model-driven development: The good, the bad, and the ugly," in IBM Systems Journal, vol. 45, no. 3, pp. 451-461, 2006. A very interesting paper on modeling during development, describing in formal way the approaches used also for the digital design.
• P. Koopman and T. Chakravarty, "Cyclic redundancy code (CRC) polynomial selection for embedded networks," International Conference on Dependable Systems and Networks, 2004, Florence, Italy, 2004, pp. 145-154. A very interesting paper on CRC properties analyzing error detection capabilities of published polynomials and proposing alternatives to some weaker ones. A must read for anybody dealing with the CRC selection for a concrete application.
• J. Doweck et al., "Inside 6th-Generation Intel Core: New Microarchitecture Code-Named Skylake," in IEEE Micro, vol. 37, no. 2, pp. 52-62, Mar.-Apr. 2017. doi: 10.1109/MM.2017.38 An interesting insight into high-end CPU design, its features and performance.
• Clifford Cummings, "SystemVerilog's priority & unique - A Solution to Verilog's "full_case" & "parallel_case" Evil Twins!",In SNUG San Jose 2006. Some words on the usage of the unique and priority in SystemVerilog for the synthesizable code.

Web resources

• The laws of software design
• DeepChip pages.Really interesting information, subscribe to their mailing list!
• The Embedded Muse A really interesting server about embedded development, they also send an interesting newsletter.
• Lots of interesting papers on sunburst-design.com
• Introduction to Verilog
  Short introduction to the Verilog language. Some things are missing, but as introduction it is more than sufficient. It also explains what is and what is not synthesizable.
• Možnosti realizace pamětí RAM v obvodech FPGA.
  
• HDL Coding Practices to Accelerate Design Performance
• OpenCores - Open IP Cores
• http://www.fpga4fun.com/
• FPGA designs from Scratch
• VHDL Cookbook
• VHDL mini reference
• VHDL Tutorial

CPU design

• J. Doweck et al., "Inside 6th-Generation Intel Core: New Microarchitecture Code-Named Skylake," in IEEE Micro, vol. 37, no. 2, pp. 52-62, Mar.-Apr. 2017. doi: 10.1109/MM.2017.38 An interesting insight into high-end CPU design, its features and performance.
• T. Singh et al., "Zen: An Energy-Efficient High-Performance x86 Core," in IEEE Journal of Solid-State Circuits, vol. 53, no. 1, pp. 102-114, Jan. 2018, doi: 10.1109/JSSC.2017.2752839. A case study of a modern CPU design with the adaptive clocking: clock is slowed down when the power supply drop is detected.
• C. Gonzalez et al., "The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4," in IEEE Journal of Solid-State Circuits, vol. 53, no. 1, pp. 91-101, Jan. 2018, doi: 10.1109/JSSC.2017.2748623.Another intereseting case study of a CPU with adaptive clocking.
• Dobberpuhl, Daniel W.; Supnik, Robert M.; Witek, Richard T. (March 1986). "The MicroVAX 78032 Chip, A 32-Bit Microprocessor". Digital Technical Journal. Digital Equipment Corporation. 1 (2): 13–24. An interesting case study describing conversion of a multi-chip minicomputer in a single ASIC. The ASIC design had to be area-efficient, so a software emulation technique was used to implement some rarely used complex instructions present in the previous design. A parallel with the RISC CPUs can be seen, here.
• Bidermann, William R.; Fisher, Amnon; Leary, Burton M.; Simcoe, Robert J.; Wheeler, William R. (March 1986). "The MicroVAX 78132 Floating Point Chip". Digital Technical Journal. Digital Equipment Corporation. 1 (2): 25–37. Another case study, this time of a Floating point coprocessor with plenty of details of the design. Although an old paper, it is worth reading.
• Y. Lee et al., "An Agile Approach to Building RISC-V Microprocessors," in IEEE Micro, vol. 36, no. 2, pp. 8-20, Mar.-Apr. 2016, doi: 10.1109/MM.2016.11. A case study of an agile approach applied on the RISC-V microprocessor design. Walking skeleton approach used, where features were added on the go as time allowed to add them; also the approach taken to the prototyping is described, there.
• K. Ma et al., "Nonvolatile Processor Architectures: Efficient, Reliable Progress with Unstable Power," in IEEE Micro, vol. 36, no. 3, pp. 72-83, May-June 2016, doi: 10.1109/MM.2016.35. An interesting concept of a CPU allowing short on-off cycles utilizing non-volatile cells to store intermediate values is described in the paper (see other papers refenced by it for more details) along with some analysis of potential architectonical solutions.
• K. C. Yeager, "The Mips R10000 superscalar microprocessor," in IEEE Micro, vol. 16, no. 2, pp. 28-41, April 1996, doi: 10.1109/40.491460. Description of the architecture of a superscalar CPU with plenty of details.

Design For Test, Testing, and related topics

• V. D. Agrawal, C. R. Kime and K. K. Saluja, "A tutorial on built-in self-test. I. Principles," in IEEE Design & Test of Computers, vol. 10, no. 1, pp. 73-82, March 1993. doi: 10.1109/54.199807 A nice introduction to the Built-In Self Test techniques. The paper is a bit older, but still capturing well the basics and worth reading.
• V. D. Agrawal, C. R. Kime and K. K. Saluja, "A tutorial on built-in self-test. 2. Applications," in IEEE Design & Test of Computers, vol. 10, no. 2, pp. 69-77, June 1993. doi: 10.1109/54.211530 This is the second part of the series, showing some applications and pointing to further papers. Again, the paper is a bit older, but worth reading. Only the section on the CAD tool support (in 1993) is now outdated.
• A. Carbine and D. Feltham, "Pentium Pro processor design for test and debug," in IEEE Design & Test of Computers, vol. 15, no. 3, pp. 77-82, July-Sept. 1998, doi: 10.1109/54.706037. An interesting case study on implementation of testing features in a microprocessor. It is a bit older, but still interesting reading.
• R. Molyneaux, T. Ziaja, Hong Kim, Shahryar Aryani, Sungbae Hwang and A. Hsieh, "Design for testability features of the SUN microsystems niagara2 CMP/CMT SPARC chip," 2007 IEEE International Test Conference, 2007, pp. 1-8, doi: 10.1109/TEST.2007.4437561. Case study of the DFT design in the high performance microprocessor: scan chains, MBIST, March-C for memories...

Some papers on embedded development

• N. Murphy, Watchdog timers. A short summary on how to deal with watchdog with notes on integration of it into a multitasking embedded operating system.
• Santic, John S. “Watchdog Timer Techniques,” Embedded Systems Programming, April 1995, p. 58. A primer on watchdogs with code example.
• S. Baek, S. Cho and R. Melhem, "Refresh Now and Then," in IEEE Transactions on Computers, vol. 63, no. 12, pp. 3114-3126, Dec. 2014, doi: 10.1109/TC.2013.164. Summary of techniques used to refresh the dynamic RAMs and ideas how to make the refresh more low-power.

Others

• PsPAD text editor for Windows
• Visual Studio Code editor
• Morse programs for Windows
• Android games and applications

Some papers on logic design of mine

• J. Šťastný, High performance cross-correlator, in Preprints, IFAC Workshop On Programmable Devices And Systems, Ostrava, Czech Republic, pp. 184 189, February 11-13, 2003.
• Jakub Šťastný and Petr Bílý, An FPGA Microcontroller Design, Elektrorevue, no. 30, 2006.
  • Česká verze
  • English version of the article
• M. Machalec, J. Šťastný. Synchronous FSM Design Methodology for Low Power Smart Sensors and RFID Devices, Elektrorevue, 15.09.2010, ISSN 1213-1539
• J. Kubák, J. Šťastný, P. Kujan. Programmable PWM modulator optimized for high speed for OPWM test platform. In Applied Electronics, Applied Electronics, pp 157-160, September 2014.
• M. Dřínovský, J. Šťastný. Implementation of the serial arithmetic operators on the modern field programmable gate array devices,  Elektrorevue, no 32., 2009
• J. Kubak, J. Stastny, P. Sovka. An Embedded Implementation of Discrete Zolotarev Transform Using Hardware-Software Codesign. Radioengineering, pp 364-371, June 2021. DOI: 10.13164/re.2021.0364.

Amazing Engineering

Microelectronics

• Charles J. Murray, "Who Really Invented the Rechargeable Lithium-Ion Battery?", in IEEE Spectrum, vol. 60, no. 8, pp. 40 - 45, August 2023. History of the invention describing a long and winding road from the first idea to the mass production.
• Keith A. Bowman, "A Circuit to Boost Battery Life", in IEEE Spectrum. Digital low-dropout voltage regulators will save time, money, and power.
• Samuel K. Moore, "3 Ways 3D Chip Tech Is Upending Computing", in IEEE Spectrum. AMD, Graphcore, and Intel show why the industry’s leading edge is going vertical.
• A. Mantooth, C. M. Zetterling and A. Rusu, "Venus Calling Silicon Carbide Radio Circuits Can Take The Heat Needed To Phone Home From Our Hellish Sister Planet," in IEEE Spectrum, vol. 58, no. 5, pp. 24-30, May 2021, doi: 10.1109/MSPEC.2021.9423815. How to build a radio device which can whitstand the hellish conditions on Venus surface?
• Anthony F.J. Levi, Gabriel Aeppli, "The X-Ray Tech That Reveals Chip Designs," in IEEE Spectrum, vol. 59, no. 5, pp. 38-43, May 2022.X-ray–based techniques can reconstruct the interconnects in a chip layer by layer and in 3D without destroying it.
• Wavedrom tool for very quick drawing of logic timing diagrams - "waves"

Others

• Robert N.Charette, "Can Flow Batteries Finally Beat Lithium?," in IEEE Spectrum, vol. 61, issue. 2, pp. 22 - 27, February 2024. An interesting battery concept allowing a quick refuelling
• Jon D. Paul, "The Scandalous History of the Last Rotor Cipher Machine," in IEEE Spectrum, September 2021 On restoration of a crypto machine and about one interesting backdoor.
• James Webb Space Telescope has arrived at its new home – an orbit almost a million miles from Earth + some further links to other articles about the telescope.
• "Lithium batteries' big unanswered question," in BBC Future, 6.1.2022 As the world looks to electrify vehicles and store renewable power, one giant challenge looms: what will happen to all the old lithium batteries?
• M. Galucci, "Thermal Solar Goes Where PVs Can’t. Energy storage sparks a concentrating-solar boom," in IEEE Spectrum, October 2021. Solar power plant without photovoltaic; steam turbines got a new steam :-).
• E. Thomas, "Turning Letters into Tones: A century ago, the optophone allowed blind people to hear the printed word," in IEEE Spectrum, vol. 58, no. 7, pp. 34-39, July 2021, doi: 10.1109/MSPEC.2021.9475413.The optophone turned letters into tones and was the proof of concept for optical character recognition. An optical character recognition technology from the beginning of the 20th century.

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